By Shu K., Sánchez-Sinencio E.
ISBN-10: 0387236694
ISBN-13: 9780387236698
ISBN-10: 1402071272
ISBN-13: 9781402071270
ISBN-10: 1402072384
ISBN-13: 9781402072383
ISBN-10: 1402072449
ISBN-13: 9781402072444
This booklet offers either basics and the state-of-the-art of PLL synthesizer layout and research suggestions. a whole evaluation of either system-level and circuit-level layout and research are coated. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is carried out in 0.35m m CMOS. It includes a high-speed and powerful phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which take on pace and integration bottlenecks of PLL synthesizer elegantly.This booklet is conceived as a PLL synthesizer handbook for either academia researchers and layout engineers.
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Additional resources for CMOS PLL Synthesizers: Analysis and Design
Example text
4 Frequency synthesizer for wireless transceivers Frequency synthesizers are used as local oscillators (LO) in the wireless transceivers for frequency translation and channel selection. Figure 2-13 shows the popular super-heterodyne receiver architecture [1]. It is a two-step down-conversion architecture. A tunable RF LO is for both the first step frequency conversion and channel selection, and an IF fixed-frequency LO is for further frequency down-conversion to baseband. Figure 2-13. Super-heterodyne receiver architecture Figure 2-14.
386-390 A. Rokita, “Direct analog synthesis modules for an X-band frequency source,” International Conference on Microwaves and Radar, vol. 1, May 1998, pp. 63-68 W. Egan, Frequency Synthesis by Phase Lock. John Wiley & Sons, 2000 V. Reinhardt, “Spur reduction techniques in direct digital synthesizers,” in Proc. Int. , June 1993, pp. 230-241 H. Wolfson, “Very small frequency generator systems for spread spectrum EHF applications,” MILCOM’89, vol. 3, Oct. 1989, pp. 749-753 J. Nieznanski, “An alternative approach to the ROM-less direct digital synthesis,” IEEE J.
3-7 (a), is: 3. PLL FREQUENCY SYNTHESIZER 37 where is the zero in the loop filter for loop stability. 14) we know that the closed loop gain has a low-pass characteristic. It is equal to the frequency divide ratio N when or It is reduced by 3dB at Table 3-2 lists the relationship between factor Note that unity gain frequency ratio and the damping and as in this book we refer to the PLL open-loop as the PLL bandwidth. The natural frequency to crossover frequency ratio factor versus phase margin is plotted in Fig.
CMOS PLL Synthesizers: Analysis and Design by Shu K., Sánchez-Sinencio E.
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